CSE 30 -- Lecture 6 -- Oct 13


The processor-to-memory pathway is actually a little more complex in modern systems. There is a cache that sits between the processor and the system bus:

The cache contains associative memory -- think of this as tables containing address and cache line pairs, where a cache line is several contiguous words of memory (32-128 bytes). When the processor load from memory, the cache is first consulted; the load address are compared against all the addresses in the cache (in parallel), and if a copy of the memory word is in the cache, that copy can be quickly returned to the processor: the cache memory is typically implemented from SRAM (Static Random Access Memory), which is faster than DRAM but is more expensive and less dense. This is known as a cache hit. If, on the other hand, there are no copies in cache memory, the cache will forward the memory load request to the DRAM (actually, the cache will load an entire cache line). This is known as a cache miss. The expected time to do a load is t = thit p + tmiss (1-p), where p is the probability of a cache hit. When expressed as a percent, p is also called the hit rate. Most programs have good locality of reference, which makes having a cache improve throughput (another way to look at it is that p tends to be high through the execution of the program).

Missing from this web page are answers to: "why the first time you load a variable's contents you do not necessarily incur a cache miss?", "why is there locality of reference?", "what are the factors that affect p?", "what are the factors that affect the values of thit and tmiss in a system?" You should find out the answers to these questions, from the book or from discussions with your fellow classmates. Make sure you understand the reason behind the answers -- don't just memorize them.


The MIPS is a RISC. It has 32 general purpose registers. Most instructions deal with registers only; MIPS is a load/store architecture. The reason for adopting a load/store architecture is performance -- the complexity of handling interrupts (I/O devices, page faults, etc) is isolated to a few instructions, since most others are single-cycle instructions.

More on this later.

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